nvSRAM 4 Click is based on the CY14B101PA, a 1-Mbit nvSRAM memory organized as 128K words of 8 bits each, with a fully-featured real-time clock from Cypress Semiconductor. The nvSRAM specifies one million endurance cycles for nonvolatile cells with data retention of a minimum of 20 years. All the reads and writes to nvSRAM happen to the SRAM, which gives nvSRAM the unique capability to handle infinite writes to the memory. The benefit of nvSRAM over serial EEPROMs is that all reads and writes to nvSRAM are performed at the SPI speed with zero cycle delay, which means, therefore, no wait time is required after any of the memory accesses.

In addition to the CY14B101PA, this Click board™ is equipped with the button cell battery holder compatible with the 3000TR battery holder, suitable for 12mm Coin Cell batteries. When the primary power fails and drops below 2.65V, this Click board™ switches to the backup power supply by placing a jumper labeled as RTC-BATT. By utilizing an automatic backup, the CY14B101PA uses an external battery power source when there is no power supply on its main power terminals allowing for uninterrupted operation.

nvSRAM 4 Click communicates with MCU using a standard SPI interface with clock frequency up to 40MHz, zero cycle delay read, and write cycles. It also supports the two most common modes, SPI Mode 0 and 3, and 104 MHz SPI access speed with special instruction for the read operation. The CY14B101PA uses the standard SPI opcodes for memory access. In addition to the general SPI instructions for reading and writing, it provides four special instructions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).

The STORE operation of the CY14B101PA can be controlled and acknowledged via the HSB pin, routed on the RST pin of the mikroBUS™ socket. If no STORE/RECALL is in progress, this pin can be used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101PA conditionally initiates a STORE operation. Also, this Click board™ can use the AutoStore feature of the SRAM data in nonvolatile cells when the power goes down, providing power-down data security by placing a jumper labeled as RTC-CAP.

An additional feature of this Click board™ represents the configurable Write Protection function labeled as WP routed on the PWM pin of the mikroBUS™ socket. The WP pin protects the entire memory and all registers from write operations and must be held high to inhibit all the write operations. When this pin is high, all memory and register writes are prohibited, and the address counter is not incremented. Besides, the nvSRAM 4 Click also has additional HOLD and Interrupt pins, routed to the AN and INT pins of the mikroBUS™ socket labeled as HLD and INT.

HLD pin is used to pause the serial communication without stopping the operation of write status register, programming, or erasing in progress. On the other hand, INT pin can be used in several ways such as interrupt output, calibration, or a square wave, programmable to respond to the clock alarm, the watchdog timer, and the power monitor.

This Click board™ is designed to be operated only with a 3.3V logic voltage level. A proper logic voltage level conversion should be performed before the Click board™ is used with MCUs with different logic levels. However, Mikroe equipped its users with a library that contains functions and an example code that can be used, as a reference, for further development.